TCAD simulation of tunnel FET devices

• Main Author: Ang, Ming Hao
• Other Authors: Pey Kin Leong
• Format: Final Year Project
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
• Online Access: http://hdl.handle.net/10356/17964
• Institution: Nanyang Technological University

As the conventional metal oxide semiconductor field-effect transistor (MOSFET) keep scaling down to a sub-micron dimension, it became a serious problem. To overcome this problem, devices based on tunneling currents have been proposed as the candidate of MOSFET. The tunnel field-effect transistor (TFET) is a three-terminal gate-controlled p-i-n diode with intrinsic region on top of the MOS-gate. It has several advantages over the conventional MOSFET. The advantages are 1. Suitable for low power application because of lower leakage current. 2. Absence of short-channel effects (SCE) and because of their resulting low off-currents. 3. The sub-threshold slope can be less than 60 mV/decade, such that potentially lower supply voltages can be used. 4. The tunneling effect and the velocity overshoot may enhance the device operating speed. 5. Much smaller Vt roll-off while scaling because threshold voltage of TFET depends on the band bending in small tunnel region, but not the whole channel region. 6. The channel region can be an intrinsic silicon which suppresses the Vt fluctuation caused by dopant atoms random distribution. 7. No punch-through effect in TFET because of reverse p-i-n structure. In this thesis, the device simulations are carried out using a 2-demensional device simulator, Taurus MEDICI. A simulation model is developed to simulate the current-voltage (I-V) characteristics and define the electrical parameters of the devices. Single-gate Si/SiGe TFET and double-gate Si/SiGe TFET are simulated. From the simulated results, the high performance TFET required thin gate oxide tox, abrupt doping profile and heavy source doped concentration. SiGe is used to lower the tunnel barrier height to enhance the performance. Compare double-gate TFET with Single-gate TFET, it has lower subthreshold swing S, threshold voltage Vt and leakage current. Therefore, with the extremely low leakage current and subthreshold swing S, TFET is the promising candidate for future scaled CMOS technologies for both ultra low power and high speed applications.