Integrating and simulating NVDLA with a RISC-V core in RTL
This project focuses on integrating and simulating the NVIDIA Deep Learning Accelerator (NVDLA) with a RISC-V based microcontroller, PULPissimo, to create a reliable deep learning and neural network system. This report will also serve as a comprehensive guide for users looking to implement NVDLA...
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| Format: | Final Year Project |
| Language: | English |
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Nanyang Technological University
2024
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| Online Access: | https://hdl.handle.net/10356/180991 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | This project focuses on integrating and simulating the NVIDIA Deep Learning Accelerator
(NVDLA) with a RISC-V based microcontroller, PULPissimo, to create a
reliable deep learning and neural network system. This report will also serve as a comprehensive
guide for users looking to implement NVDLA with PULPissimo, which
offers a detailed documentation and insights into the integration process.
The primary objective involves the integration of NVDLA’s Configuration Space Bus
(CSB) with PULPissimo’s Advanced Peripheral Bus (APB), enabling system communication.
The implementation process includes synthesising the integrated system, running tests
on multiple iterations and ensuring stability and performance for the whole system.
While initial results show successful integration and execution, the system stalls after
several iterations, highlighting a critical stability issues. This work identifies bottlenecks
and proposes optimisations to enhance the system’s stability |
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