Integrating and simulating NVDLA with a RISC-V core in RTL
This project focuses on integrating and simulating the NVIDIA Deep Learning Accelerator (NVDLA) with a RISC-V based microcontroller, PULPissimo, to create a reliable deep learning and neural network system. This report will also serve as a comprehensive guide for users looking to implement NVDLA...
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Nanyang Technological University
2024
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sg-ntu-dr.10356-1809912024-11-11T00:50:18Z Integrating and simulating NVDLA with a RISC-V core in RTL Lim, Nicholas Jan Tuck Mohamed M. Sabry Aly College of Computing and Data Science msabry@ntu.edu.sg Engineering This project focuses on integrating and simulating the NVIDIA Deep Learning Accelerator (NVDLA) with a RISC-V based microcontroller, PULPissimo, to create a reliable deep learning and neural network system. This report will also serve as a comprehensive guide for users looking to implement NVDLA with PULPissimo, which offers a detailed documentation and insights into the integration process. The primary objective involves the integration of NVDLA’s Configuration Space Bus (CSB) with PULPissimo’s Advanced Peripheral Bus (APB), enabling system communication. The implementation process includes synthesising the integrated system, running tests on multiple iterations and ensuring stability and performance for the whole system. While initial results show successful integration and execution, the system stalls after several iterations, highlighting a critical stability issues. This work identifies bottlenecks and proposes optimisations to enhance the system’s stability Bachelor's degree 2024-11-11T00:50:18Z 2024-11-11T00:50:18Z 2024 Final Year Project (FYP) Lim, N. J. T. (2024). Integrating and simulating NVDLA with a RISC-V core in RTL. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/180991 https://hdl.handle.net/10356/180991 en SCSE23-1141 application/pdf Nanyang Technological University |
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Engineering Lim, Nicholas Jan Tuck Integrating and simulating NVDLA with a RISC-V core in RTL |
| description |
This project focuses on integrating and simulating the NVIDIA Deep Learning Accelerator
(NVDLA) with a RISC-V based microcontroller, PULPissimo, to create a
reliable deep learning and neural network system. This report will also serve as a comprehensive
guide for users looking to implement NVDLA with PULPissimo, which
offers a detailed documentation and insights into the integration process.
The primary objective involves the integration of NVDLA’s Configuration Space Bus
(CSB) with PULPissimo’s Advanced Peripheral Bus (APB), enabling system communication.
The implementation process includes synthesising the integrated system, running tests
on multiple iterations and ensuring stability and performance for the whole system.
While initial results show successful integration and execution, the system stalls after
several iterations, highlighting a critical stability issues. This work identifies bottlenecks
and proposes optimisations to enhance the system’s stability |
| author2 |
Mohamed M. Sabry Aly |
| author_facet |
Mohamed M. Sabry Aly Lim, Nicholas Jan Tuck |
| format |
Final Year Project |
| author |
Lim, Nicholas Jan Tuck |
| author_sort |
Lim, Nicholas Jan Tuck |
| title |
Integrating and simulating NVDLA with a RISC-V core in RTL |
| title_short |
Integrating and simulating NVDLA with a RISC-V core in RTL |
| title_full |
Integrating and simulating NVDLA with a RISC-V core in RTL |
| title_fullStr |
Integrating and simulating NVDLA with a RISC-V core in RTL |
| title_full_unstemmed |
Integrating and simulating NVDLA with a RISC-V core in RTL |
| title_sort |
integrating and simulating nvdla with a risc-v core in rtl |
| publisher |
Nanyang Technological University |
| publishDate |
2024 |
| url |
https://hdl.handle.net/10356/180991 |
| _version_ |
1816858926462795776 |