Design of a scalable RF model for deep sub-micron mosfets

• Main Author: Tong, Ah Fatt
• Other Authors: Yeo Kiat Seng
• Format: Theses and Dissertations
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Semiconductors
• Online Access: https://hdl.handle.net/10356/20850
• Institution: Nanyang Technological University

In order to achieve first pass design success and optimized RF circuit design, the process design kit (PDK) provided by the foundry must be equipped with accurate and scalable RF models for circuit simulation and optimization process. However, existing RF MOSFET models provided by most foundries are usually in discrete sizes. This poses many design problems for the integrated circuit (IC) designers because certain transistors’ geometry sizes are not available in the PDK. Design optimization is not possible without scalable RFCMOS models and the circuit performance cannot be optimized for a particular technology node used for circuit fabrication. Furthermore, discrete RFCMOS models will limit the design flexibility and increase the difficulty in designing RF circuit blocks to meet more stringent design specifications as the operating frequency increases. Currently in the industry, the RF MOSFET model that was developed is mainly in BSIM3v3 and BSIM4 models. In BSIM3v3, the RF model is developed by macro modeling approach whereby sub-circuit components are added to the core transistor model. In BSIM4, the RF model for the parasitic components were developed and included into the source code of the core model. Therefore, theoretically, there is no need for the addition of the sub-circuit components as in BSIM3v3 RF model. Although these two RF models are able to simulate the transistor’s S-parameters, the sub-circuit components used are of discrete values. Thus, scalable RF modeling is still not achieved. Therefore, there is a need to study how to develop a scalable and physical RF MOSFET model.