FPGA implementation of low density parity-check (LDPC) coded recording channels

• 主要作者: Seyed Mohammad Ehsan Hosseini
• 其他作者: Chan Kheong Sann
• 格式: Theses and Dissertations
• 語言: English
• 出版: 2010
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• 在線閱讀: https://hdl.handle.net/10356/20856
• 機構: Nanyang Technological University

Low Density Parity-Check (LDPC) codes have received lots of attention during the past decade due to their near Shannon-limit performance and decoding at very high rates. However, several issues have been raised in the research work with an aim to achieve the practical implementation of the LDPC code...