FPGA implementation of low density parity-check (LDPC) coded recording channels
Low Density Parity-Check (LDPC) codes have received lots of attention during the past decade due to their near Shannon-limit performance and decoding at very high rates. However, several issues have been raised in the research work with an aim to achieve the practical implementation of the LDPC code...
محفوظ في:
| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | |
| التنسيق: | Theses and Dissertations |
| اللغة: | English |
| منشور في: |
2010
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| الموضوعات: | |
| الوصول للمادة أونلاين: | https://hdl.handle.net/10356/20856 |
| الوسوم: |
إضافة وسم
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| المؤسسة: | Nanyang Technological University |
| اللغة: | English |