FPGA implementation of low density parity-check (LDPC) coded recording channels

• المؤلف الرئيسي: Seyed Mohammad Ehsan Hosseini
• مؤلفون آخرون: Chan Kheong Sann
• التنسيق: Theses and Dissertations
• اللغة: English
• منشور في: 2010
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/20856

Low Density Parity-Check (LDPC) codes have received lots of attention during the past decade due to their near Shannon-limit performance and decoding at very high rates. However, several issues have been raised in the research work with an aim to achieve the practical implementation of the LDPC code...