Hot carrier reliability perspective on silicon-on-insulator lateral double-diffused MOSFET (LDMOS)

• Main Author: Liao, Jie
• Other Authors: Tan Cher Ming
• Format: Theses and Dissertations
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Semiconductors
• Online Access: https://hdl.handle.net/10356/20920
• Institution: Nanyang Technological University

Silicon-on-insulator (SOI) device has a buried silicon oxide (Buried Oxide, or BOX) layer extending across the entire wafer. Recently, there is an increased interest in SOI wafers for application to the fabrication of advanced CMOS ICs. SOI technologies offer a large number of advantages in terms of capacitances, less cross-talk and high integration density [1]. One of the most common power MOSFETs used in smart power applications is SOI lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) because of its high speed, low on-state resistance, as well as the fabrication processes are compatible with the standard low voltage CMOS process [2]. The performance of the SOI LDMOSFET is increased dramatically compared to the bulk technologies. However, SOI LDMOSFET is prone to hot carrier induced (HCI) degradation because the high operational voltages applied to the drain and/or gate will degrade the device electrical performance after prolonged operation. Many researches showed that the hot carrier reliability of a device is strongly dependent on its geometrical configuration, operational conditions, as well as the process parameters [3-5].