Resolving and guardbanding backend impact for poly plug incomplete barrier contact for SDRAM

Aggressive downscaling leads to increasing density for DRAM (Dynamic Random Access Memory) chips, resulting in higher probability of failure. In this MSc dissertation a key process issue, poly plug incomplete barrier contact (IBC) related to a DRAM yield loss of 3-4% was explored. Both electrical fa...

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Main Author: Tan, Albert Chong Kit
Other Authors: Lau, Wai Shing
Format: Theses and Dissertations
Published: 2008
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Online Access:http://hdl.handle.net/10356/3339
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Institution: Nanyang Technological University
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spelling sg-ntu-dr.10356-33392023-07-04T15:19:31Z Resolving and guardbanding backend impact for poly plug incomplete barrier contact for SDRAM Tan, Albert Chong Kit Lau, Wai Shing School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Microelectronics Aggressive downscaling leads to increasing density for DRAM (Dynamic Random Access Memory) chips, resulting in higher probability of failure. In this MSc dissertation a key process issue, poly plug incomplete barrier contact (IBC) related to a DRAM yield loss of 3-4% was explored. Both electrical failure analysis (EFA) and physical failure analysis (PFA) techniques were applied to tackle this problem. The root cause was successfully identified as incomplete contact hole etch for (a) the contact hole between the digitline (bitline) and the memory cell transistor and (b) the contact hole between the memory cell transistor and the memory cell capacitor, resulting in either open circuit or high resistance. Master of Science (Microelectronics) 2008-09-17T09:27:47Z 2008-09-17T09:27:47Z 2003 2003 Thesis http://hdl.handle.net/10356/3339 Nanyang Technological University application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
topic DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
Tan, Albert Chong Kit
Resolving and guardbanding backend impact for poly plug incomplete barrier contact for SDRAM
description Aggressive downscaling leads to increasing density for DRAM (Dynamic Random Access Memory) chips, resulting in higher probability of failure. In this MSc dissertation a key process issue, poly plug incomplete barrier contact (IBC) related to a DRAM yield loss of 3-4% was explored. Both electrical failure analysis (EFA) and physical failure analysis (PFA) techniques were applied to tackle this problem. The root cause was successfully identified as incomplete contact hole etch for (a) the contact hole between the digitline (bitline) and the memory cell transistor and (b) the contact hole between the memory cell transistor and the memory cell capacitor, resulting in either open circuit or high resistance.
author2 Lau, Wai Shing
author_facet Lau, Wai Shing
Tan, Albert Chong Kit
format Theses and Dissertations
author Tan, Albert Chong Kit
author_sort Tan, Albert Chong Kit
title Resolving and guardbanding backend impact for poly plug incomplete barrier contact for SDRAM
title_short Resolving and guardbanding backend impact for poly plug incomplete barrier contact for SDRAM
title_full Resolving and guardbanding backend impact for poly plug incomplete barrier contact for SDRAM
title_fullStr Resolving and guardbanding backend impact for poly plug incomplete barrier contact for SDRAM
title_full_unstemmed Resolving and guardbanding backend impact for poly plug incomplete barrier contact for SDRAM
title_sort resolving and guardbanding backend impact for poly plug incomplete barrier contact for sdram
publishDate 2008
url http://hdl.handle.net/10356/3339
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