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Implementation of digital systems on FPGA devices

The objective of the project is to design and synthesize both a master and slave PCI local bus, so that they can be reused if other design requires a PCI bus. The design in this work is based on PCI local bus specification rev 3.0. VERILOG HDL is chosen to implement the design in RTL level. The PCI...

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書目詳細資料
主要作者: Chen, Lan.
其他作者: Jong, Ching Chuen
格式: Theses and Dissertations
出版: 2008
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在線閱讀:http://hdl.handle.net/10356/3793
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