Implementation of digital systems on FPGA devices

The objective of the project is to design and synthesize both a master and slave PCI local bus, so that they can be reused if other design requires a PCI bus. The design in this work is based on PCI local bus specification rev 3.0. VERILOG HDL is chosen to implement the design in RTL level. The PCI...

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Bibliographic Details
Main Author: Chen, Lan.
Other Authors: Jong, Ching Chuen
Format: Theses and Dissertations
Published: 2008
Subjects:
Online Access:http://hdl.handle.net/10356/3793
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Institution: Nanyang Technological University