CMOS building blocks for 10+Gb/s clock data recovery circuit
157 p.
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2010
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| Institution: | Nanyang Technological University |
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sg-ntu-dr.10356-390322023-07-04T17:31:43Z CMOS building blocks for 10+Gb/s clock data recovery circuit Liu, Haiqi Goh Wang Ling School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits 157 p. The design of a clock data recovery (CDR) circuit is the most challenging part of building a high-speed optical transceiver because of the complexity of this block. In this dissertation, the design of a half-rate high speed CDR is described, following a top-down design procedure. VHDL-AMS, which is the acronym of the VHDL (VHSIC Hardware Description Language) for Analog and Mixed-Signal, is used to implement the behavioral model of the whole system in the early and mid-stage of the design process. DOCTOR OF PHILOSOPHY (EEE) 2010-05-21T04:37:46Z 2010-05-21T04:37:46Z 2007 2007 Thesis Liu, H. (2007). CMOS building blocks for 10Gb/s clock data recovery circuit. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/39032 10.32657/10356/39032 application/pdf |
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Nanyang Technological University |
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Singapore Singapore |
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DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits |
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DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Liu, Haiqi CMOS building blocks for 10+Gb/s clock data recovery circuit |
| description |
157 p. |
| author2 |
Goh Wang Ling |
| author_facet |
Goh Wang Ling Liu, Haiqi |
| format |
Theses and Dissertations |
| author |
Liu, Haiqi |
| author_sort |
Liu, Haiqi |
| title |
CMOS building blocks for 10+Gb/s clock data recovery circuit |
| title_short |
CMOS building blocks for 10+Gb/s clock data recovery circuit |
| title_full |
CMOS building blocks for 10+Gb/s clock data recovery circuit |
| title_fullStr |
CMOS building blocks for 10+Gb/s clock data recovery circuit |
| title_full_unstemmed |
CMOS building blocks for 10+Gb/s clock data recovery circuit |
| title_sort |
cmos building blocks for 10+gb/s clock data recovery circuit |
| publishDate |
2010 |
| url |
https://hdl.handle.net/10356/39032 |
| _version_ |
1772828338217287680 |