Low power low voltage adder cells for digital multiplier
As battery operated devices prevail, power consumption in digital signal processor has emerged as an increasingly critical design constraint in addition to the pursuit of timing closure and area efficiency. Addition and multiplication, being the fundamental arithmetic operations in digital signal pr...
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| Format: | Theses and Dissertations |
| Published: |
2008
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| Online Access: | http://hdl.handle.net/10356/3990 |
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| Institution: | Nanyang Technological University |
| Summary: | As battery operated devices prevail, power consumption in digital signal processor has emerged as an increasingly critical design constraint in addition to the pursuit of timing closure and area efficiency. Addition and multiplication, being the fundamental arithmetic operations in digital signal processors and microprocessors, are subjects of perpetual research interest in VLSI design. This thesis deals with the design of low power high performance arithmetic circuits through design innovation and optimization in a bottom-up approach begins at the transistor level. |
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