Low power low voltage adder cells for digital multiplier

Low power low voltage adder cells for digital multiplier

As battery operated devices prevail, power consumption in digital signal processor has emerged as an increasingly critical design constraint in addition to the pursuit of timing closure and area efficiency. Addition and multiplication, being the fundamental arithmetic operations in digital signal pr...

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Main Author: Zhang, Mingyan
Other Authors: Chang, Chip Hong
Format: Theses and Dissertations
Published: 2008
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Online Access:http://hdl.handle.net/10356/3990
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Institution: Nanyang Technological University
id sg-ntu-dr.10356-3990
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spelling sg-ntu-dr.10356-39902023-07-04T15:07:47Z Low power low voltage adder cells for digital multiplier Zhang, Mingyan Chang, Chip Hong School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits As battery operated devices prevail, power consumption in digital signal processor has emerged as an increasingly critical design constraint in addition to the pursuit of timing closure and area efficiency. Addition and multiplication, being the fundamental arithmetic operations in digital signal processors and microprocessors, are subjects of perpetual research interest in VLSI design. This thesis deals with the design of low power high performance arithmetic circuits through design innovation and optimization in a bottom-up approach begins at the transistor level. Master of Engineering 2008-09-17T09:41:59Z 2008-09-17T09:41:59Z 2004 2004 Thesis http://hdl.handle.net/10356/3990 Nanyang Technological University application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
topic DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Zhang, Mingyan
Low power low voltage adder cells for digital multiplier
description As battery operated devices prevail, power consumption in digital signal processor has emerged as an increasingly critical design constraint in addition to the pursuit of timing closure and area efficiency. Addition and multiplication, being the fundamental arithmetic operations in digital signal processors and microprocessors, are subjects of perpetual research interest in VLSI design. This thesis deals with the design of low power high performance arithmetic circuits through design innovation and optimization in a bottom-up approach begins at the transistor level.
author2 Chang, Chip Hong
author_facet Chang, Chip Hong
Zhang, Mingyan
format Theses and Dissertations
author Zhang, Mingyan
author_sort Zhang, Mingyan
title Low power low voltage adder cells for digital multiplier
title_short Low power low voltage adder cells for digital multiplier
title_full Low power low voltage adder cells for digital multiplier
title_fullStr Low power low voltage adder cells for digital multiplier
title_full_unstemmed Low power low voltage adder cells for digital multiplier
title_sort low power low voltage adder cells for digital multiplier
publishDate 2008
url http://hdl.handle.net/10356/3990
_version_ 1772828123072561152

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