FPGA implementation of a speech coder

In this project, one of the speech compression methods, a LPC 10 decoder was designed by using VHDL. In the designed LPC decoder, two different types of speech production model were designed and used to compare their performances. The first model used two adders, two multipliers and one substractor...

全面介紹

Saved in:
書目詳細資料
主要作者: Tay, Zar Myint.
其他作者: Ho Duan Juat
格式: Final Year Project
語言:English
出版: 2010
主題:
在線閱讀:http://hdl.handle.net/10356/40567
標簽: 添加標簽
沒有標簽, 成為第一個標記此記錄!