FPGA implementation of a speech coder

• 主要作者: Tay, Zar Myint.
• 其他作者: Ho Duan Juat
• 格式: Final Year Project
• 語言: English
• 出版: 2010
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing
• 在線閱讀: http://hdl.handle.net/10356/40567
• 機構: Nanyang Technological University

In this project, one of the speech compression methods, a LPC 10 decoder was designed by using VHDL. In the designed LPC decoder, two different types of speech production model were designed and used to compare their performances. The first model used two adders, two multipliers and one substractor and the second one used four multipliers, four adders and one substractor. It was found that the first model took three cycles more than the second one to complete the one sample. On the other hand, the first model only used total 19778 gates while the second one used 28901 gates. Therefore the second model took more resources. After completing the speech production model, real speech parameters are used to feed into the speech production model and simulated to generate synthesis speech. The reconstructed speech signal was able to achieve the original signal at reasonable quality. In order to analyze the performance of the designed speech production model, another speech production model was created by using Microsoft Excel, which used exact fraction value of LPC parameters and the output speech signal was used as a model answer of a LPC speech production. The LPC parameters such as coefficients, pitch, vice information and gain were estimated by using MatLab. After feeding parameters into speech production model, the result speech signals are put in Matlab to generate the waveform and carried out the analyzing and comparison. Comparing to original speech, the pitches of simulated signal and amplitudes were different from original due to constant value of estimated parameter value in 20ms frame. The error was analyzed and found that the error occurred due to binary representation.