Modeling of PCI with SystemVerilog
Deep submicron semiconductor technology has enabled system-level IC design complexity to exceed millions of gates. This presents a major design and verification challenge that intensifies the demand for system-level design languages. A major impact in solving this problem has been the development...
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| Format: | Theses and Dissertations |
| Published: |
2008
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| Online Access: | http://hdl.handle.net/10356/4142 |
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| Institution: | Nanyang Technological University |
| Summary: | Deep submicron semiconductor technology has enabled system-level IC design
complexity to exceed millions of gates. This presents a major design and verification
challenge that intensifies the demand for system-level design languages. A major impact in solving this problem has been the development and standardization of an Hardware Description and Verification Language like SystemVerilog which caters all the needs for design as well as verification. |
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