Modeling of PCI with SystemVerilog

Deep submicron semiconductor technology has enabled system-level IC design complexity to exceed millions of gates. This presents a major design and verification challenge that intensifies the demand for system-level design languages. A major impact in solving this problem has been the development...

Full description

Saved in:

Bibliographic Details
Main Author:	Chithambaram Shaalini.
Other Authors:	Jong, Ching Chuen
Format:	Theses and Dissertations
Published:	2008
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Online Access:	http://hdl.handle.net/10356/4142
Tags:	Add Tag No Tags, Be the first to tag this record!
Institution:	Nanyang Technological University

id	sg-ntu-dr.10356-4142
record_format	dspace
spelling	sg-ntu-dr.10356-41422023-07-04T15:52:07Z Modeling of PCI with SystemVerilog Chithambaram Shaalini. Jong, Ching Chuen School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Deep submicron semiconductor technology has enabled system-level IC design complexity to exceed millions of gates. This presents a major design and verification challenge that intensifies the demand for system-level design languages. A major impact in solving this problem has been the development and standardization of an Hardware Description and Verification Language like SystemVerilog which caters all the needs for design as well as verification. Master of Science (Integrated Circuit Design) 2008-09-17T09:45:20Z 2008-09-17T09:45:20Z 2005 2005 Thesis http://hdl.handle.net/10356/4142 Nanyang Technological University application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
topic	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Chithambaram Shaalini. Modeling of PCI with SystemVerilog
description	Deep submicron semiconductor technology has enabled system-level IC design complexity to exceed millions of gates. This presents a major design and verification challenge that intensifies the demand for system-level design languages. A major impact in solving this problem has been the development and standardization of an Hardware Description and Verification Language like SystemVerilog which caters all the needs for design as well as verification.
author2	Jong, Ching Chuen
author_facet	Jong, Ching Chuen Chithambaram Shaalini.
format	Theses and Dissertations
author	Chithambaram Shaalini.
author_sort	Chithambaram Shaalini.
title	Modeling of PCI with SystemVerilog
title_short	Modeling of PCI with SystemVerilog
title_full	Modeling of PCI with SystemVerilog
title_fullStr	Modeling of PCI with SystemVerilog
title_full_unstemmed	Modeling of PCI with SystemVerilog
title_sort	modeling of pci with systemverilog
publishDate	2008
url	http://hdl.handle.net/10356/4142
_version_	1772827755367366656

Modeling of PCI with SystemVerilog

Similar Items