Digital system design with FPGA using verilog HDL

• 主要作者: Cho, Shao Ying.
• 其他作者: Jong Ching Chuen
• 格式: Final Year Project
• 語言: English
• 出版: 2011
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
• 在線閱讀: http://hdl.handle.net/10356/42749

In this final year project (Digital system design with FPGA using Verilog HDL) CORDIC is selected as the digital system to be designed. CORDIC is a simple and yet efficient algorithm for computing the hyperbolic and trigonometric functions, without the need of complex hardware multipliers and div...