Effect of thermal-induced stress on SOI power devices

• Main Author: Huang, Guangyu
• Other Authors: Tan Cher Ming
• Format: Theses and Dissertations
• Language: English
• Published: 2011
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Power electronics
• Online Access: https://hdl.handle.net/10356/42905
• Institution: Nanyang Technological University

Silicon-on-insulator (SOI) technology presents one way of fabricating semiconductor devices on an insulating substrate rather than in a semiconductor bulk. It is a promising potential technology for the next generation ULSI because of its many advantages over its bulk silicon substrate counterpart, such as immunity to radiation, reduction in parasitic capacitance, reduction in power delay product, high packing density and simplicity in manufacturing process, and elimination of metal spike etc. Owing to these advantages, SOI CMOS technology has been gradually recognized as a promising ULSI technology. In addition to ULSI application, SOI technology has also been used to realize communication circuits, microwave devices, and even fiber optics application for its superior performance. With the growing trends of the portable systems, low-voltage and low-power designs have been indispensable. In this aspect, SOI technology is suitable for integration of the low voltage and low-power VLSI circuits, because of the steeper subthreshold slope feature of SOI CMOS devices.