Design and implementation of a digital integrated circuit for logarithmic conversion (C4)

• 主要作者: Wong, Wee Kiat.
• 其他作者: Jong Ching Chuen
• 格式: Final Year Project
• 語言: English
• 出版: 2011
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• 在線閱讀: http://hdl.handle.net/10356/45908
• 機構: Nanyang Technological University

This project report describes the design of an integrated circuit to implement a logarithmic converter based on the Combet’s 4-region (C4) logarithmic conversion algorithm from the front end design (HDL coding of the design specifications) to the back end (layout). The Combet’s 4-region (C4) logarithmic conversion algorithm involves piecewise linear approximation of the mantissa, dividing the mantissa curve into 4 regions. The computation of the approximation involves simple shifting and counting operations that can be easily implemented by hardware. The design is to be described in Verilog HDL at RTL level in the Mentor Graphics Modelsim environment. Modelsim is also used for functional simulation, back annotated simulation and verification. Gate level logic synthesis will then be carried out using Synopsys Design Compiler. Various constraints are provided to optimize the area and timing of the design. The gate level netlist generated by the Design Compiler is to be used in the placement and routing of the design.