Simulation and optimisation of a tunneling field effect transistor

• Main Author: Neo, Samuel Choon Wee
• Other Authors: Zhou Xing
• Format: Final Year Project
• Language: English
• Published: 2011
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
• Online Access: http://hdl.handle.net/10356/46199
• Institution: Nanyang Technological University

This report details the operating principles and physics governing a vertical silicon nanowire (SiNW) based tunneling field effect transistor (TFET). It also explores areas in which the TFET performances could be improved and optimized. Although a SiNW based TFET has its improvements over MOSFET in certain areas, it has its own limitations. Its primary advantages over MOSFET are that its subthreshold swing is not limited to 60mV/dec and is largely temperature independent. It can also be fabricated to sub 22nm gate length with almost no drain induced barrier lowering effect, meaning it experience extremely negligible leakage current. Its general Ion/Ioff ratio is about 106 times or more. However, the biggest limitation of SiNW based TFET is its extremely low drive current. Factors affecting its drive current are explored in this report and with these critical factors in mind; ways to optimize its performance is further explored through computer aided simulations. With all its advantages of being a much smaller structure than conventional MOSFETs, meaning it can have a higher packing density and its extremely low leakage power, the SiNW based TFET is definitely a very strong candidate to become the building block of next generation’s ultra-power and high density application.