Design automation for a 2 uM double-metal CMOS gate array

143 p.

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Bibliographic Details
Main Author: Chua, Hong Chuek.
Other Authors: School of Electrical and Electronic Engineering
Format: Research Report
Published: 2011
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Online Access:http://hdl.handle.net/10356/46617
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Institution: Nanyang Technological University
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spelling sg-ntu-dr.10356-466172023-03-04T03:22:53Z Design automation for a 2 uM double-metal CMOS gate array Chua, Hong Chuek. School of Electrical and Electronic Engineering DRNTU::Engineering::Mechanical engineering 143 p. The objective of this project is to develop an electronic design automation (EDA) package for the 2 \im CMOS base array which was previously designed by the joint effort of both staff and students of the School of EEE, NTU. The development work followed closely the requirements of the industry in ASIC design. The three design streams, A, B and C, have been developed and successfully implemented on the Mentor Graphics Workstation. RP 30/87 2011-12-21T03:07:38Z 2011-12-21T03:07:38Z 1992 1992 Research Report http://hdl.handle.net/10356/46617 Nanyang Technological University application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
topic DRNTU::Engineering::Mechanical engineering
spellingShingle DRNTU::Engineering::Mechanical engineering
Chua, Hong Chuek.
Design automation for a 2 uM double-metal CMOS gate array
description 143 p.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Chua, Hong Chuek.
format Research Report
author Chua, Hong Chuek.
author_sort Chua, Hong Chuek.
title Design automation for a 2 uM double-metal CMOS gate array
title_short Design automation for a 2 uM double-metal CMOS gate array
title_full Design automation for a 2 uM double-metal CMOS gate array
title_fullStr Design automation for a 2 uM double-metal CMOS gate array
title_full_unstemmed Design automation for a 2 uM double-metal CMOS gate array
title_sort design automation for a 2 um double-metal cmos gate array
publishDate 2011
url http://hdl.handle.net/10356/46617
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