Design automation for a 2 uM double-metal CMOS gate array
143 p.
Saved in:
Main Author: | Chua, Hong Chuek. |
---|---|
Other Authors: | School of Electrical and Electronic Engineering |
Format: | Research Report |
Published: |
2011
|
Subjects: | |
Online Access: | http://hdl.handle.net/10356/46617 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Similar Items
-
Metal gate for advanced CMOS applications
by: Lai, Donny Jiancheng
Published: (2010) -
Experimental modules on integrated circuit design using tanner for 0.18um CMOS process
by: Amis, Paul Anthony M., et al.
Published: (2014) -
CMOS electrodes array for DNA binding
by: Loh, Kah Meng.
Published: (2008) -
Experimental modules on integrated circuit design using tanner for 0.25 um, 0.35 um, and 0.5 CMOS process
by: Escano, Ron Alvin V., et al.
Published: (2010) -
Phase-locked loop for low frequency application using 0.18um CMOS technology
by: Zhang, Yao.
Published: (2009)