Design of process variation-tolerant circuits

• Main Author: Ho, Kim Ming.
• Other Authors: School of Electrical and Electronic Engineering
• Format: Final Year Project
• Language: English
• Published: 2012
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electric power
• Online Access: http://hdl.handle.net/10356/50088
• Institution: Nanyang Technological University

This report emphasises on the 6T Static Random Access Memory (SRAM). It describes the basic theory of the SRAM, the concepts of measuring degradation in digital circuits as well as effects of wordline modulation to mitigate the impact of the combined effect of Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) on SRAM Vmin. This report consists of two parts. First the student discuss the design, schematic and layout, of basic blocks for frequency degradation monitor in digital circuits. Secondly, the student analyse the impacts of NBTI and PBTI on 6T SRAM Vmin and present a new design technique to alleviate the impacts of NBTI and PBTI on SRAM. Simulations results show that the wordline voltage together with pulse width control can mitigate the transistor degradation caused by NBTI and PBTI.