Watermark insertion and detection through embedded test machine for VLSI IP protection
IP watermarking is an efficient and economical approach to IP protection. In this project, a rather simple testability-driven partitioning method for large gate-level circuits is used for watermarking. The algorithm decomposes a single machine into an interconnection of component machines, each havi...
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| Format: | Final Year Project |
| Language: | English |
| Published: |
2012
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| Online Access: | http://hdl.handle.net/10356/50141 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | IP watermarking is an efficient and economical approach to IP protection. In this project, a rather simple testability-driven partitioning method for large gate-level circuits is used for watermarking. The algorithm decomposes a single machine into an interconnection of component machines, each having a constant number of flip-flops. Watermark bits are inserted by incorporating the test function into each component. This method of decomposing a large machine into small components and incorporating testability in each component substantially reduces the time complexity of synthesis. The algorithm is verified and the partition is implemented in C++ program. |
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