Watermark insertion and detection through embedded test machine for VLSI IP protection

Watermark insertion and detection through embedded test machine for VLSI IP protection

IP watermarking is an efficient and economical approach to IP protection. In this project, a rather simple testability-driven partitioning method for large gate-level circuits is used for watermarking. The algorithm decomposes a single machine into an interconnection of component machines, each havi...

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Main Author: Che, Xuerong.
Other Authors: Chang Chip Hong
Format: Final Year Project
Language:English
Published: 2012
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Online Access:http://hdl.handle.net/10356/50141
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-501412023-07-07T16:54:03Z Watermark insertion and detection through embedded test machine for VLSI IP protection Che, Xuerong. Chang Chip Hong School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits IP watermarking is an efficient and economical approach to IP protection. In this project, a rather simple testability-driven partitioning method for large gate-level circuits is used for watermarking. The algorithm decomposes a single machine into an interconnection of component machines, each having a constant number of flip-flops. Watermark bits are inserted by incorporating the test function into each component. This method of decomposing a large machine into small components and incorporating testability in each component substantially reduces the time complexity of synthesis. The algorithm is verified and the partition is implemented in C++ program. Bachelor of Engineering 2012-05-30T04:14:05Z 2012-05-30T04:14:05Z 2012 2012 Final Year Project (FYP) http://hdl.handle.net/10356/50141 en Nanyang Technological University 72 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Che, Xuerong.
Watermark insertion and detection through embedded test machine for VLSI IP protection
description IP watermarking is an efficient and economical approach to IP protection. In this project, a rather simple testability-driven partitioning method for large gate-level circuits is used for watermarking. The algorithm decomposes a single machine into an interconnection of component machines, each having a constant number of flip-flops. Watermark bits are inserted by incorporating the test function into each component. This method of decomposing a large machine into small components and incorporating testability in each component substantially reduces the time complexity of synthesis. The algorithm is verified and the partition is implemented in C++ program.
author2 Chang Chip Hong
author_facet Chang Chip Hong
Che, Xuerong.
format Final Year Project
author Che, Xuerong.
author_sort Che, Xuerong.
title Watermark insertion and detection through embedded test machine for VLSI IP protection
title_short Watermark insertion and detection through embedded test machine for VLSI IP protection
title_full Watermark insertion and detection through embedded test machine for VLSI IP protection
title_fullStr Watermark insertion and detection through embedded test machine for VLSI IP protection
title_full_unstemmed Watermark insertion and detection through embedded test machine for VLSI IP protection
title_sort watermark insertion and detection through embedded test machine for vlsi ip protection
publishDate 2012
url http://hdl.handle.net/10356/50141
_version_ 1772828500709867520

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