Electrical characterization of the novel vertical slit field-effect transistor (VeSFET)
A junctionless Vertical Slit Field-Effect Transistor (VeSFET) fabricated on SOI wafer using conventional CMOS process was proposed by W. Maly, et al.[1]. This new architecture device has two symmetrical independent gates with a three-dimensional channel. This device structure is to overcome the chal...
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| Format: | Final Year Project |
| Language: | English |
| Published: |
2012
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| Online Access: | http://hdl.handle.net/10356/50177 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | A junctionless Vertical Slit Field-Effect Transistor (VeSFET) fabricated on SOI wafer using conventional CMOS process was proposed by W. Maly, et al.[1]. This new architecture device has two symmetrical independent gates with a three-dimensional channel. This device structure is to overcome the challenges faced in scaling down the size of transistor, such as short-channel effect faced by conventional MOSFET. |
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