Electrical characterization of the novel vertical slit field-effect transistor (VeSFET)

Electrical characterization of the novel vertical slit field-effect transistor (VeSFET)

A junctionless Vertical Slit Field-Effect Transistor (VeSFET) fabricated on SOI wafer using conventional CMOS process was proposed by W. Maly, et al.[1]. This new architecture device has two symmetrical independent gates with a three-dimensional channel. This device structure is to overcome the chal...

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Main Author: Tung, Zhi Yan.
Other Authors: Ang Diing Shenp
Format: Final Year Project
Language:English
Published: 2012
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Electric power
Online Access:http://hdl.handle.net/10356/50177
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-501772023-07-07T15:56:56Z Electrical characterization of the novel vertical slit field-effect transistor (VeSFET) Tung, Zhi Yan. Ang Diing Shenp School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electric power A junctionless Vertical Slit Field-Effect Transistor (VeSFET) fabricated on SOI wafer using conventional CMOS process was proposed by W. Maly, et al.[1]. This new architecture device has two symmetrical independent gates with a three-dimensional channel. This device structure is to overcome the challenges faced in scaling down the size of transistor, such as short-channel effect faced by conventional MOSFET. Bachelor of Engineering 2012-05-30T08:17:17Z 2012-05-30T08:17:17Z 2012 2012 Final Year Project (FYP) http://hdl.handle.net/10356/50177 en Nanyang Technological University 72 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Electric power
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Electric power
Tung, Zhi Yan.
Electrical characterization of the novel vertical slit field-effect transistor (VeSFET)
description A junctionless Vertical Slit Field-Effect Transistor (VeSFET) fabricated on SOI wafer using conventional CMOS process was proposed by W. Maly, et al.[1]. This new architecture device has two symmetrical independent gates with a three-dimensional channel. This device structure is to overcome the challenges faced in scaling down the size of transistor, such as short-channel effect faced by conventional MOSFET.
author2 Ang Diing Shenp
author_facet Ang Diing Shenp
Tung, Zhi Yan.
format Final Year Project
author Tung, Zhi Yan.
author_sort Tung, Zhi Yan.
title Electrical characterization of the novel vertical slit field-effect transistor (VeSFET)
title_short Electrical characterization of the novel vertical slit field-effect transistor (VeSFET)
title_full Electrical characterization of the novel vertical slit field-effect transistor (VeSFET)
title_fullStr Electrical characterization of the novel vertical slit field-effect transistor (VeSFET)
title_full_unstemmed Electrical characterization of the novel vertical slit field-effect transistor (VeSFET)
title_sort electrical characterization of the novel vertical slit field-effect transistor (vesfet)
publishDate 2012
url http://hdl.handle.net/10356/50177
_version_ 1772825697908162560

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