Low-power and robust SRAM design

Low-power and robust SRAM design

This thesis pertains to the design of low power and robust SRAMs without significant area overhead and speed penalty. Novel designs are presented to reduce the power dissipation by using dynamic voltage scaling as well as reducing the power dissipation on large capacitive metal lines, for example bi...

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書目詳細資料
主要作者:	Chen, Junchao.
其他作者:	Gwee Bah Hwee
格式:	Theses and Dissertations
語言:	English
出版:	2013
主題:	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
在線閱讀:	http://hdl.handle.net/10356/51690
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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