Characterization of semiconductor process parameters

• Main Author: Gan, Chin Ngap
• Other Authors: Yoon Soon Fatt
• Format: Final Year Project
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Microelectronics; DRNTU::Engineering::Materials::Material testing and characterization; DRNTU::Engineering::Electrical and electronic engineering::Semiconductors
• Online Access: http://hdl.handle.net/10356/53005
• Institution: Nanyang Technological University

Silicon, being the most mature technology in the electronics industry, is facing limitations and challenges that threaten to displace Moore’s Law as device sizes get increasingly smaller. The monolithic integration of III-V to Silicon via wafer bonding will marry the advantages of both platforms for the realization of optoelectronic integrated circuits. However, due to the severe thermal expansion mismatch, high temperature processes cannot be performed on thick, industrial scale size wafer. In this study, 2 inch Silicon bonded to Gallium-Arsenide wafers using the plasma activated direct wafer bonding technique is chemical-mechanical polished on the GaAs backside and was able to reach to an average thickness of 60µm. Thinning rate of 4µm/min and surface roughness of 1.5~1.6nm were achieved through the current efforts. Through this study, a pair of thinned down Si to GaAs bonded sample can go through high temperature molecular beam epitaxy process for device structure growth.