Low power CMOS parallel prefix adders
Addition is the basic operation in many modern electronic applications. As the fastest adder, parallel prefix adder is of most interest for many circuit designers. For the past few decades, supply voltage and the size of transistors have been reduced tremendously. With more and...
Saved in:
Main Author: | Yang, Shaochen |
---|---|
Other Authors: | Lau Kim Teen |
Format: | Theses and Dissertations |
Language: | English |
Published: |
2013
|
Subjects: | |
Online Access: | http://hdl.handle.net/10356/54882 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
Low power high performance CMOS adder design
by: Wen, Han
Published: (2019) -
Low power 32-bit full adders in 65nm CMOS technology
by: Kumar, Praveen.
Published: (2014) -
Quaternary quantum/reversible half-adder, full-adder, parallel adder and parallel adder/subtractor circuits
by: Monfared, Asma Taheri, et al.
Published: (2021) -
Performance analysis and comparison of low power dynamic and differential CMOS logic adder circuits
by: Prasanna Dhayalan
Published: (2015) -
Ultra-low power 8-bit CMOS adder design based on approximate arithmetic
by: Hu, Zhengyu
Published: (2019)