Moire measurement of IC packages

• Main Author: Huang, Xia.
• Other Authors: Yi, Sung
• Format: Theses and Dissertations
• Published: 2008
• Subjects: DRNTU::Engineering::Manufacturing
• Online Access: http://hdl.handle.net/10356/5804
• Institution: Nanyang Technological University

Flip-chip components have been studied under thermal-cycles. An ultra sensitive displacement measuring technique Moire interferometry was used to investigate this phenomenon. The Moire interferometer was incorporated with a heating chamber whereby the real-time observation of the thermal-cycle process can be done. Flip-chip consists of three layers, the bottom layer is RF-4 substrate, middle and top layers being silicon and molding compound, respectively. Due to the difference in the coefficient of thermal expansion (CTE) of these three layers, the flip-chip will undergo warpage upon thermal cycling. In this experiment, the deformation was recorded using Moire system along the U, V and W fields respectively, and the thermo-mechanical behavior of flip-chip is characterized. The flip-chip structure has the thickness much smaller compared to the in-plane dimensions. This fact is used to build up a flip-chip warpage calculation model. This model assumes the out-of-plane deformation being smaller than the thickness of the flip-chip. It also assumes that the curvature is the same everywhere and the strains are axisymmetric. Out-of-plane deformation formula is derived and is calculated using an Excel spreadsheet.