Asynchronous logic quasi delay insensitive (QDI) static/dynamic/pass logic transistor-level implementation half/full buffer realization approaches for robust VLSI system
This report targeted to explore the characteristics of different types of asynchronous logic quasi-delay-insensitive circuit design. High performance electronic circuit is the main design goal for current technology. However, the performance of traditional synchronous logic circuit is often limit...
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| Format: | Final Year Project |
| Language: | English |
| Published: |
2014
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| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/60438 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | This report targeted to explore the characteristics of different types of asynchronous logic
quasi-delay-insensitive circuit design. High performance electronic circuit is the main design
goal for current technology. However, the performance of traditional synchronous logic
circuit is often limited by the global clock signal. Asynchronous logic should be the future
direction of logic design that have the potential to overcome this issue. In this project, five
types of asynchronous design technique, which included Static/Dynamic/Pass Logic
Transistor-level Implementation, Pre-Charged Half-Buffer and Weak-Conditioned Half-
Buffer and four key parameters, which included Delay, Power consumption, Energy
consumption and Number of transistor used were experimented. The results of this project
showed each type of design technique has its unique characteristic. A complete comparison
table is included in the appendix to provide a clear comparison of the results obtained in this
project. |
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