Asynchronous logic quasi delay insensitive (QDI) static/dynamic/pass logic transistor-level implementation half/full buffer realization approaches for robust VLSI system

This report targeted to explore the characteristics of different types of asynchronous logic quasi-delay-insensitive circuit design. High performance electronic circuit is the main design goal for current technology. However, the performance of traditional synchronous logic circuit is often limit...

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Bibliographic Details
Main Author: Tsui, Yun Kan
Other Authors: Gwee Bah Hwee
Format: Final Year Project
Language:English
Published: 2014
Subjects:
Online Access:http://hdl.handle.net/10356/60438
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Institution: Nanyang Technological University
Language: English

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