Asynchronous logic quasi delay insensitive (QDI) static/dynamic/pass logic transistor-level implementation half/full buffer realization approaches for robust VLSI system

• المؤلف الرئيسي: Tsui, Yun Kan
• مؤلفون آخرون: Gwee Bah Hwee
• التنسيق: Final Year Project
• اللغة: English
• منشور في: 2014
• الموضوعات: DRNTU::Engineering
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/60438
• المؤسسة: Nanyang Technological University

This report targeted to explore the characteristics of different types of asynchronous logic quasi-delay-insensitive circuit design. High performance electronic circuit is the main design goal for current technology. However, the performance of traditional synchronous logic circuit is often limit...