Asynchronous logic quasi delay insensitive (QDI) static/dynamic/pass logic transistor-level implementation half/full buffer realization approaches for robust VLSI system
This report targeted to explore the characteristics of different types of asynchronous logic quasi-delay-insensitive circuit design. High performance electronic circuit is the main design goal for current technology. However, the performance of traditional synchronous logic circuit is often limit...
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| 主要作者: | |
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| 格式: | Final Year Project |
| 語言: | English |
| 出版: |
2014
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| 主題: | |
| 在線閱讀: | http://hdl.handle.net/10356/60438 |
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| 機構: | Nanyang Technological University |
| 語言: | English |