Process induced reliability of through silicon via

• Main Author: Zhang, Jiye
• Other Authors: Tan Chuan Seng
• Format: Theses and Dissertations
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
• Online Access: https://hdl.handle.net/10356/61812
• Institution: Nanyang Technological University

Insatiable consumer demand for multifunctional and high performance integrated circuits and systems has necessitated three-dimensional (3D) integration with through silicon via (TSV) technology. 3D integration has provided a scaling path to reduce the wire length and power consumption. At the same t...