Low power asynchronous 8051 implementation and evaluation

With the increasing demand for low power device in consumer electronics and biomedical field, the requirement and constraint for designing low power chip also increase. Due to the presence of clock network and clock skew, the larger chip area in design, such as microcontroller, presents the...

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Main Author: Ne Kyaw Zwa Lwin
Other Authors: School of Electrical and Electronic Engineering
Format: Theses and Dissertations
Language:English
Published: 2015
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Online Access:http://hdl.handle.net/10356/65139
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-651392023-07-04T15:24:25Z Low power asynchronous 8051 implementation and evaluation Ne Kyaw Zwa Lwin School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Applications of electronics With the increasing demand for low power device in consumer electronics and biomedical field, the requirement and constraint for designing low power chip also increase. Due to the presence of clock network and clock skew, the larger chip area in design, such as microcontroller, presents the increasing difficulty in reliable clock network. Asynchronous design technique offers the alternative to this problem with its absence of a clock signal. Besides, it also provides other benefits in terms of power and robustness in a wide range of power and Process-Voltage-Temperature (PVT) variation. This thesis pertains to the design, implementation and evaluation of a low power asynchronous 8051 microcontroller for low power applications. The low power aspect of the microcontroller is based on the asynchronous methodology and voltage scaling. The asynchronous 8051 microcontroller is implemented using STM 45nm CMOS technology and integrated with ROM, RAM and XRAM blocks. The custom-designed asynchronous SRAM is used for all three memory blocks. The core design is based on the Balsa netlist, a synthesizing language for asynchronous systems. The microcontroller and asynchronous SRAM are tested and evaluated. The SRAM is able to operate down to the lowest voltage of 0.25V. It is also found that SRAM can operate at maximum of 150 MHz and minimum of 79 KHz respectively at nominal 1 V and 0.25V. The asynchronous 8051 microcontroller has 50% and 93% power reduction from nominal voltage when voltage is scaled down to 0.8V and 0.4V respectively. The power efficiency of the microcontroller can also be boosted by 13% through scaling the supply voltage down to 0.8V. Master of Science (Electronics) 2015-06-15T04:01:50Z 2015-06-15T04:01:50Z 2014 2014 Thesis http://hdl.handle.net/10356/65139 en 66 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Applications of electronics
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Applications of electronics
Ne Kyaw Zwa Lwin
Low power asynchronous 8051 implementation and evaluation
description With the increasing demand for low power device in consumer electronics and biomedical field, the requirement and constraint for designing low power chip also increase. Due to the presence of clock network and clock skew, the larger chip area in design, such as microcontroller, presents the increasing difficulty in reliable clock network. Asynchronous design technique offers the alternative to this problem with its absence of a clock signal. Besides, it also provides other benefits in terms of power and robustness in a wide range of power and Process-Voltage-Temperature (PVT) variation. This thesis pertains to the design, implementation and evaluation of a low power asynchronous 8051 microcontroller for low power applications. The low power aspect of the microcontroller is based on the asynchronous methodology and voltage scaling. The asynchronous 8051 microcontroller is implemented using STM 45nm CMOS technology and integrated with ROM, RAM and XRAM blocks. The custom-designed asynchronous SRAM is used for all three memory blocks. The core design is based on the Balsa netlist, a synthesizing language for asynchronous systems. The microcontroller and asynchronous SRAM are tested and evaluated. The SRAM is able to operate down to the lowest voltage of 0.25V. It is also found that SRAM can operate at maximum of 150 MHz and minimum of 79 KHz respectively at nominal 1 V and 0.25V. The asynchronous 8051 microcontroller has 50% and 93% power reduction from nominal voltage when voltage is scaled down to 0.8V and 0.4V respectively. The power efficiency of the microcontroller can also be boosted by 13% through scaling the supply voltage down to 0.8V.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Ne Kyaw Zwa Lwin
format Theses and Dissertations
author Ne Kyaw Zwa Lwin
author_sort Ne Kyaw Zwa Lwin
title Low power asynchronous 8051 implementation and evaluation
title_short Low power asynchronous 8051 implementation and evaluation
title_full Low power asynchronous 8051 implementation and evaluation
title_fullStr Low power asynchronous 8051 implementation and evaluation
title_full_unstemmed Low power asynchronous 8051 implementation and evaluation
title_sort low power asynchronous 8051 implementation and evaluation
publishDate 2015
url http://hdl.handle.net/10356/65139
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