Design of minimum energy driven ultra-low voltage SRAMs and D flip-flop
The aggressive CMOS technology shrinking driven by cost reduction, performance improvement and power minimization enables integration of billions of transistors onto a single chip. State-of-the-art System-on-Chips (SoCs) incorporate more cores, larger capacity caches and more application-specific ha...
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| 格式: | Theses and Dissertations |
| 出版: |
2015
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| 在線閱讀: | https://hdl.handle.net/10356/65355 |
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| 機構: | Nanyang Technological University |