Non-imprinting high-speed erase SRAM IC design for low-power operation
This report discusses the design and characterization process and result of a novel SRAM: Non-imprinting High-speed Erase SRAM (NIHE SRAM). By erasing data clearly and instantly, the developed NIHE SRAM can be used to store highly confidential information. The first part of the report will review...
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| Format: | Final Year Project |
| Language: | English |
| Published: |
2016
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| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/67773 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | This report discusses the design and characterization process and result of a novel SRAM:
Non-imprinting High-speed Erase SRAM (NIHE SRAM). By erasing data clearly and
instantly, the developed NIHE SRAM can be used to store highly confidential information.
The first part of the report will review the conventional 6T SRAM design methodology
and its figures of merit. In the second part, the NIHE SRAM cell operation will be
discussed first, followed by the simulation result and analysis. Finally, the report will
present the optimized version of NIHE SRAM cell’s layout. The NIHE SRAM cell was
developed using Global Foundry 65nm technology. |
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