Non-imprinting high-speed erase SRAM IC design for low-power operation
This report discusses the design and characterization process and result of a novel SRAM: Non-imprinting High-speed Erase SRAM (NIHE SRAM). By erasing data clearly and instantly, the developed NIHE SRAM can be used to store highly confidential information. The first part of the report will review...
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| Online Access: | http://hdl.handle.net/10356/67773 |
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sg-ntu-dr.10356-677732023-07-07T17:03:45Z Non-imprinting high-speed erase SRAM IC design for low-power operation Bian, Jia Kun Gwee Bah Hwee School of Electrical and Electronic Engineering DRNTU::Engineering This report discusses the design and characterization process and result of a novel SRAM: Non-imprinting High-speed Erase SRAM (NIHE SRAM). By erasing data clearly and instantly, the developed NIHE SRAM can be used to store highly confidential information. The first part of the report will review the conventional 6T SRAM design methodology and its figures of merit. In the second part, the NIHE SRAM cell operation will be discussed first, followed by the simulation result and analysis. Finally, the report will present the optimized version of NIHE SRAM cell’s layout. The NIHE SRAM cell was developed using Global Foundry 65nm technology. Bachelor of Engineering 2016-05-20T05:25:56Z 2016-05-20T05:25:56Z 2016 Final Year Project (FYP) http://hdl.handle.net/10356/67773 en Nanyang Technological University 55 p. application/pdf |
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Asia |
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DRNTU::Engineering Bian, Jia Kun Non-imprinting high-speed erase SRAM IC design for low-power operation |
| description |
This report discusses the design and characterization process and result of a novel SRAM:
Non-imprinting High-speed Erase SRAM (NIHE SRAM). By erasing data clearly and
instantly, the developed NIHE SRAM can be used to store highly confidential information.
The first part of the report will review the conventional 6T SRAM design methodology
and its figures of merit. In the second part, the NIHE SRAM cell operation will be
discussed first, followed by the simulation result and analysis. Finally, the report will
present the optimized version of NIHE SRAM cell’s layout. The NIHE SRAM cell was
developed using Global Foundry 65nm technology. |
| author2 |
Gwee Bah Hwee |
| author_facet |
Gwee Bah Hwee Bian, Jia Kun |
| format |
Final Year Project |
| author |
Bian, Jia Kun |
| author_sort |
Bian, Jia Kun |
| title |
Non-imprinting high-speed erase SRAM IC design for low-power operation |
| title_short |
Non-imprinting high-speed erase SRAM IC design for low-power operation |
| title_full |
Non-imprinting high-speed erase SRAM IC design for low-power operation |
| title_fullStr |
Non-imprinting high-speed erase SRAM IC design for low-power operation |
| title_full_unstemmed |
Non-imprinting high-speed erase SRAM IC design for low-power operation |
| title_sort |
non-imprinting high-speed erase sram ic design for low-power operation |
| publishDate |
2016 |
| url |
http://hdl.handle.net/10356/67773 |
| _version_ |
1772826169732759552 |