Fabrication and characterization of Algan/Gan high electron mobility transistors on silicon

• Main Author: Tham, Wai Hoe
• Other Authors: Lakshimi Kanta Bera
• Format: Theses and Dissertations
• Language: English
• Published: 2016
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Semiconductors
• Online Access: https://hdl.handle.net/10356/67970
• Institution: Nanyang Technological University

“Moore’s Law” states that the number of transistors in an integrated circuit will double approximately every two years. True to this observation, the number of transistors per Si IC indeed has doubled every 18 months since the 1970s. In accordance with the scaling trend predicted in Moore’s Law, not only is the packing density of transistors increased but devices’ performance are significantly improved as well. However as the size of transistors continuously shrinks, several issues such as the fundamental limitation of Si, quantum physics of carrier transport, severity of short channel effects and lithography challenges need to be taken into consideration. Examples of these limitations can be seen in the power density and clock speed of silicon CMOS processors, where it hits saturation at about 100 W/cm2 and 4 GHz respectively. Owing to such limitations, the margin of improvement achieved by transistor scaling is no longer substantial. Thus, the global semiconductor industry has looked towards the direction of More than Moore (MtM) where both analog and digital functionalities are incorporated into a System-on-chip (SoC) platform for higher system values. For this to materialize, alternative materials with superior properties are explored in the manufacturing of semiconductor devices. Semiconductors with wide band gap properties such as the III-V compound, SiC and diamond have been successfully used in high power electronic applications. Among the III-V compounds, Gallium Nitride (GaN) is a promising alternative due to its superior inherent material properties. With its large band gap, high breakdown field, coupled with high 2DEG carrier density and superior saturation velocity, the properties of GaN offer excellent device performance, thus attracting significant attention from the next generation of optoelectronics, RF communications and high power applications. In the fabrication of high electron mobility transistors (HEMTs), it is essential to have device grade AlGaN/GaN heterostructure layers. Generally, the AlGaN/GaN epitaxy layers are mostly grown on foreign substrates such as sapphire and silicon carbide (SiC) due to the current unavailability of large high quality single crystal bulk GaN substrates. Both sapphire and SiC substrates exhibit impressive device performance, but neither offers a clear commercialization pathway due to high growth cost and limited wafer size. Therefore, strong GaN epitaxy research and development efforts which focus on silicon substrates are being pursued, which are primarily motivated by the low cost and scalability of silicon, as well as the well-established Si CMOS process. Unfortunately, the large lattice and thermal mismatch between Si and GaN introduce high threading dislocations, cracking and bowing issues in the substrates. Thus, substantial development have been carried out to grow high quality and crack-free GaN on Si wafers, including thick bulk Si and thin Silicon-on-insulator (SOI) substrates. In this dissertation, one of the main objectives is to focus on the study and comparison of AlGaN/GaN HEMTs performances on both bulk Si and thin SOI substrates using the standard gold base contact. This paper also aims to discuss the AlGaN/GaN heterostructures growth properties on both substrates, where its properties have been studied and documented. GaN on SOI wafers are found to exhibit lower wafer bowing (~50%) and lower defect density as per High Resolution X-ray Diffraction (HRXRD) analysis. Owing to the reduced bowing and lower epilayer defects, an improvement in the 2DEG mobility and sheet-resistivity uniformity across the SOI wafers is observed. The HEMT test structures fabricated on SOI substrates exhibit ~20.5% higher drain saturation current and ~19.5% higher peak transconductance as compared to bulk Si. The channel temperature profiles for both substrates have also been investigated using the micro Raman method. Results showed that HEMTs on SOI have a higher channel temperature which is ascribed to the lower thermal conduction of the buried oxide (BOX) layer. Nevertheless with the mitigation of self-heating, GaN-on-SOI substrates is deemed to be an excellent alternative in the Si integration technology. AlGaN/GaN HEMT is normally-on (depletion mode) in nature due to the existing 2DEG channel which is induced by the strong polarization charges from the AlGaN/GaN heterostructure. A normally-off (enhancement mode) device is desirable as it is able to eliminate negative power supply which reduces the overall design cost, size and complexity of the system. Several approaches in achieving Enhancement mode HEMT have been reported; such as gate recess etching, fluorine plasma treatment, and AlGaN barrier thinning. However, a standard processing method with good controllability, uniformity and reproducibility is still lacking. Therefore, another important objective of this report is to investigate the effect of Germanium diffusion on shifting the threshold voltage of AlGaN/GaN HEMT at the gate region. Si and Ge are generally used as n-type dopants in AlGaN/GaN epilayers. Similarly in Si technology, where dopants are used for threshold voltage adjustment, Ge is believed to be able to compensate the positive sheet charges on the AlGaN surface which reduces the polarization effect and hence depletes the 2DEG carrier concentration. A single RTP annealing (825 °C 60 s) is used to form the Ohmic contacts as well as to diffuse Ge into the AlGaN barrier concurrently. The fabricated Ge-diffused AlGaN/GaN HEMTs exhibit a threshold voltage shift of +1.15 V, compared to the control sample which has a threshold voltage of -3.52 V. However, there are limitations to this approach as it is constrained by the optimum temperature used in Ohmic contact processing. With higher temperature annealing, a larger positive threshold voltage shift is observed but this is at the expense of Ohmic contact and transconductance degradation coupled with a higher gate leakage. Therefore, the current experimental studies suggest that the Ge doping approach is more suitable as a VTH tuning method. Although the fabrication cost of GaN-based devices can be reduced significantly through the incorporation with Si technology, there are several challenges which impede the incorporation of GaN-based devices with Si technology. One of them is the prerequisite of Au-free low resistance CMOS compatible metal contacts. AlGaN/GaN HEMTs are typically Au-based devices where Ti/Al/Ni/Au and Ni/Au metal stacks are used as the source/drain and Gate electrodes. However, the use of highly diffusive Au is prohibited in the Si industry due to contamination risks. Moreover, Au-based contacts exhibit an overall rough surface morphology which is unfavorable for high frequency and microwave applications. Several Au-free metal schemes with good contact resistance have been reported but at the expense of high temperature annealing (>800 °C). This increases the thermal budget and limits the self-aligned gate-first process which is a mainstream approach in the Si CMOS technology. Hence in this report, a lower temperature (500 °C) process for Au-free metal scheme using (Ti/Al/NiV) contacts with a contact resistance of 0.8 Ω.mm has been demonstrated on AlGaN/GaN HEMT fabricated on Si (111) bulk substrates. The Au-free HEMT devices exhibit a smoother surface morphology and overall lower off-state current. Furthermore, excellent ION/IOFF ratio ~ 109 with a Subthreshold Swing of 71.42 mV/dec which are desirable for fast switching power applications, were observed in the fabricated devices. Therefore, we believe that the Au-free low temperature metal scheme has great prospects and potential in the fabrication of AlGaN/GaN HEMTs on Si platform. Last but not least, the performance of AlGaN/GaN HEMT is usually restricted by the severe gate leakage and high access resistance between the source and gate. In order to overcome the gate leakage issue, a MIS structure is introduced, where a high-k material is used as a gate insulator. On the other hand, access resistance can be reduced by decreasing the spacing between source/drain and gate. Nonetheless, the minimum source-to-gate access distance is constrained by the lithography tool’s capability and gate alignment issues. Hence, a self-aligned gate first process is usually preferred. Unfortunately, such gate-first process is hard to implement in GaN HEMT fabrication due to the high temperature annealing (>800 °C) needed for source/drain Ohmic contacts formation. Gate degradation and the likelihood of gate-to-drain/source shorts caused by the high thermal-budget Ohmic contact formation preclude the direct implementation of the gate-first approach in GaN HEMT fabrication. Therefore a self-aligned low temperature CMOS compatible processing is preferred. Hence in this report, an innovative self-aligned AlGaN/GaN MISHEMT fabricated using common gold-free metal and single mask for source/drain/Gate is demonstrated. Using Al2O3 as the gate dielectric, and the aforementioned low temperature gold-free metal scheme (Ti/Al/NiV), MISHEMT devices with low XI interface state density (~5 x 1011 cm-2 eV-1) coupled with good gate leakage current characteristics (sub-nA off-state leakage current at VG = -15 V) are successfully demonstrated. In addition, the fabricated MISHEMTs exhibit excellent ION/IOFF ratio and good sub threshold swing characteristics, which reflects on the good quality of our gate stack approach. Such fabrication method reduces the parasitic inhomogeneities associated with the numerous front-end processing steps and offers more flexibility in device design with limited form factor. Hence, the demonstrated novel approach is a promising alternative in gold-free GaN-on-Si integration.