A 40nm CMOS current reference with reduced PVT sensitivity

• Main Author: Prabhakar Bharath Kumar
• Other Authors: Chan Pak Kwong
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/73108
• Institution: Nanyang Technological University

A reference current is a vital building block for an analog circuit. Most often, the current reference determines the biasing point of the circuits, thereby influencing the ultimate performance of the circuitries. In this work, an improved foundation current reference with dynamic element matching (DEM) technique in 40nm CMOS technology is proposed. Not only does it improve the reported circuits in terms of process, supply voltage and temperature variations, it also enhances the immunity against the stress-induced offset arising from the stress effect on the matching pairs in the current reference circuits. The proposed work aims at designing a reference current of 2.5uA which operates with a minimum supply voltage of 1.1 V and in the temperature range of -20°C to 100°C. The extensive Monte-Carlo simulations are conducted and the results are compared with that of the prior-art works. It has shown that the proposed current reference circuit out-performs the reported works in the aspect of many performance metrics.