Design of a CMOS current-mode voltage reference with low PVT sensitivity
This dissertation proposes a new PVT-Insensitive current-mode voltage reference utilizing second-order curvature-compensated technique. Implemented in TSMC-40nm process technology, the circuit has achieved a temperature coefficient of 18 ppm/◦C in the TT corner and Monte-Carlo T.C. of 27.33 ppm/◦...
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Format: | Thesis-Master by Coursework |
Language: | English |
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Nanyang Technological University
2023
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Online Access: | https://hdl.handle.net/10356/169096 |
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Institution: | Nanyang Technological University |
Language: | English |