Design of a CMOS current-mode voltage reference with low PVT sensitivity

• Main Author: Lin, Youbo
• Other Authors: Chan Pak Kwong
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2023
• Subjects: Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/169096
• Institution: Nanyang Technological University

This dissertation proposes a new PVT-Insensitive current-mode voltage reference utilizing second-order curvature-compensated technique. Implemented in TSMC-40nm process technology, the circuit has achieved a temperature coefficient of 18 ppm/◦C in the TT corner and Monte-Carlo T.C. of 27.33 ppm/◦C from −20 ◦C to 120 ◦C, demonstrating strong temperature insensitivity. The circuit, which operates a supply voltage range of 1.1V to 1.5V, gives a 622mV output reference voltage. By utilizing subthreshold MOSFET design, the power dissipation of the circuit is about 10.8uW at a 1.2V supply voltage. The simulation results have shown that the voltage reference has attained the line sensitivity of 0.0118%/V and the PSR of -58dB at 100Hz and reaching -24dB at 10MHz. The process sensitivity of the reference voltage 3.54%. Taken into account of line sensitivity, temperature span of 100 degree C and process sensitivity, the FOM for reference voltage is obtained as 3.71%. In view of circuit simplicity and low PVT sensitivity, the proposed circuit will be very useful of high precision analog circuit applications.