Design of a CMOS current-mode voltage reference with low PVT sensitivity
This dissertation proposes a new PVT-Insensitive current-mode voltage reference utilizing second-order curvature-compensated technique. Implemented in TSMC-40nm process technology, the circuit has achieved a temperature coefficient of 18 ppm/◦C in the TT corner and Monte-Carlo T.C. of 27.33 ppm/◦...
Saved in:
Main Author: | |
---|---|
Other Authors: | |
Format: | Thesis-Master by Coursework |
Language: | English |
Published: |
Nanyang Technological University
2023
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/169096 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Be the first to leave a comment!