Power optimization in clock tree synthesis

• Main Author: Jagirdar Agathya
• Other Authors: Gwee Bah Hwee
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/73133
• Institution: Nanyang Technological University

Among the most challenging tasks of advanced-node IC design is power reduction. In the advanced technology nodes, clock trees have become a prominent source of dynamic power dissipation constituting of almost 15-21 % of the total power dissipation which is about 30-40 mW in the chip dependent on the design. Thus clock tree synthesis (CTS) and clock tree power optimization are an important task for achieving overall power savings. Conventional low power CTS strategies such as using integrated clock gates, reducing the leaf capacitance, minimizing the switching activity, and minimizing area by reducing the buffer count in the clock tree helps in improving the power profile of the chip, but they are not sufficient to meet the aggressive power targets for the advanced technology nodes. CTS engines in the EDA tools primarily aim to achieve a zero skew by balancing the latency of a signal across all the registers regardless of which level of the clock tree they belong to. However, it is not necessary for the CTS engine to balance all the clock endpoints with each other. The groups have different clock end points and do not have valid timing path, better known as skew groups. Synopsys IC Compiler tool which is used to perform placement and routing (PnR) has a special feature building clock tree with the skew group information. The aim of the project is to develop a Smart Clock Power Reduction (SCPR) algorithm which will analyze the interaction of all the flops being driven by a particular clock and come up with the skew groups for that particular clock domain. Use the generated skew groups in the Synopsys IC compiler to build the clock tree. With the skew group information the aim is to eliminate the insertion of the buffer used to balance the group of registers which can be safely skipped from being balanced and hence reduce about 10-15% which is about 5-10 mW reduction of the overall dynamic power dissipation. Also, try to analyze the corner cases were the SCPR algorithm fails to deliver expected results.