Power optimization in clock tree synthesis

• Main Author: Jagirdar Agathya
• Other Authors: Gwee Bah Hwee
• Format: Theses and Dissertations
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/73133
• Institution: Nanyang Technological University

Among the most challenging tasks of advanced-node IC design is power reduction. In the advanced technology nodes, clock trees have become a prominent source of dynamic power dissipation constituting of almost 15-21 % of the total power dissipation which is about 30-40 mW in the chip dependent on the...