A very-low dropout regulator

• Main Author: Aung Phyoe Htut
• Other Authors: Chan Pak Kwong
• Format: Final Year Project
• Language: English
• Published: 2018
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/74615
• Institution: Nanyang Technological University

The design and simulation of a low-dropout regulator (LDO) with a dynamic biasing circuit, which is used to improve transient response, closed-loop bandwidth and loop gain, is presented in this report. With additional quiescent current utilized by dynamic biasing circuit, the primary LDO achieves faster transient behavior and loop gain. The benchmark LDO is based on the Q-reduction compensation technique which enhances the stability. In this project, the improved LDO regulator is designed using TSMC 40nm technology. From the comparative simulations results, the additional dynamic biasing circuit in this work has improved transient behavior such as overshoot voltage, undershoots voltage and settling time. The whole LDO consumes quiescent current range from 94.07 ~ 159 μA for the full load current range up to 100mA. It operates at a nominal supply voltage of 1.2V with dropout voltage of 0.2V at the output voltage of 1V.